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e product preview information in this document is provided solely to enable use of intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. information contained herein supersedes previously published specifications on these devices from intel. ? intel corporation 1995 september 1995 order number: 290539-002 intel smartvoltage technology ? ? 5v or 12v program/erase ? ? 2.7v, 3.3v or 5v read operation ? ? program time reduced 60% at 12v v pp very high performance read ? ? 5v: 70/120 ns max. access time, 30/40 ns max. output enable time ? ? 3v: 120/150 ns max access 65 ns max. output enable time ? ? 2.7v: 120 ns max access 65 ns max. output enable time low power consumption ? ? max 60 ma read current at 5v ? ? max 30 ma read current at 2.7?3.6v x8/x16-selectable input/output bus ? ? 28f800 for high performance 16- or 32-bit cpus x8-only input/output architecture ? ? 28f008b for space-constrained 8-bit applications optimized array blocking architecture ? ? one 16-kb protected boot block ? ? two 8-kb parameter blocks ? ? one 96-kb main block ? ? seven 128-kb main blocks ? ? top or bottom boot locations absolute hardware-protection for boot block software eeprom emulation with parameter blocks extended temperature operation ? ? ?40c to +85c extended cycling capability ? ? 100,000 block erase cycles (commercial temperature) ? ? 10,000 block erase cycles (extended temperature) automated word/byte write and block erase ? ? industry-standard command user interface ? ? status registers ? ? erase suspend capability sram-compatible write interface automatic power savings feature ? ? 1 ma typical i cc active current in static operation reset/deep power-down input ? ? 0.2 a i cc typical ? ? provides reset for boot operations hardware data protection feature ? ? erase/write lockout during power transitions industry-standard surface mount packaging ? ? 40-lead tsop ? ? 44-lead psop: jedec rom compatible ? ? 48-lead tsop footprint upgrad eable from 2-mbit and 4-mbit boot block flash memories etox? iv flash technology 8-mbit (512k x 16, 1024k x 8) smartvoltage boot block flash memory family 28f800bv-t/b, 28f800cv-t/b, 28f008bv -t/b 28f800ce-t/b, 28f008be -t/b
8-mbit smartvoltage boot block flash memory family e 2 product preview contents page page 1.0 product family overview . 3 1.1 new features in the smartvoltage products ..................... 3 1.2 main features ................................ ... 4 1.3 applications ................................ ..... 7 1.4 pinouts ................................ .............. 8 1.5 pin descriptions ............................. 10 2.0 product description ........... 13 2.1 memory organization .................... 13 2.1.1 blocking ................................ ... 13 3.0 product family principles of operation ............................. 12 3.1 bus operations ............................... 16 3.2 read operations ............................. 16 3.2.1 read array ............................... 16 3.2.2 intelligent identifiers ................ 14 3.3 write operations ............................ 19 3.3.1 command user interface .......... 19 3.3.2 status register .......................... 17 3.3.3 program mode .......................... 18 3.3.4 erase mode .............................. 27 3.4 boot block locking ....................... 19 3.4.1 v pp = v il for complete protection ................................ .. 28 3.4.2 wp# = v il for boot block locking ................................ ..... 28 3.4.3 rp# = v hh or wp# = v ih for boot block unlocking .............. 29 3.5 power consumption ....................... 33 3.5.1 active power ............................ 33 3.5.2 automatic power savings ........ 33 3.5.3 standby power ......................... 33 3.5.4 deep power-down mode ......... 33 3.6 power-up/down operation ............ 34 3.6.1 rp# connected to system reset 34 3.6.2 v cc , v pp and rp# transtions ... 34 3.7 power supply decoupling .............. 34 3.7.1 v pp trace on printed circuit boards ................................ ...... 35 4.0 absolute maximum ratings 36 5.0 commercial operating conditions ................................ . 37 5.1 applying v cc voltages .................. 37 5.2 dc characteristics .......................... 38 5.3 ac characteristics .......................... 32 6.0 extended operating conditions ................................ . 57 6.1 applying v cc voltages .................. 57 6.2 dc characteristics .......................... 58 6.3 ac characteristics .......................... 67 7.0 additional information ... 75 7.1 ordering information ..................... 75 7.2 references ................................ ...... 77 7.3 revision history ............................ 77
e 8-mbit smartvoltage boot block flash memory family 3 product preview 1. 0 product family overview this datasheet contains the specifications for the two branches of products in the smartvoltage 8 -mbit boot block flash memory family: the -be/ce suffix products feature a low v cc operating range of 2.7?3.6v; the -bv/cv suffix products offer 3.0?3.6v operation. both be/ce and bv/cv products also operate at 5v for high-speed access times. throughout this datasheet, the 28f800 refers to all x8/x16 8 -mbit products, while 28f008b refers to all x8 8 -mbit boot block products (but not to the 28f008sa flashfile? memory). also, the term ?2.7v? generally means the full voltage range 2.7?3.6v. section 1 provides an overview of the flash memory family including applications, pinouts and pin descriptions. sections 2 and 3 describe the memory organization and operation for these products. finally, sections 4, 5 and 6 contain the family?s operating specifications. 1.1 new features in the smartvoltage products the new 8 -mbit smartvoltage boot block flash memory family provides a convenient density upgrade path from the 2-mbit and 4-mbit boot block products. the 8 -mbit boot block functions similarly to lower density boot block products in both command sets and operation, providing similar pinouts to ease density upgrades. to upgrade from lower density -bx/bl- suffix 12v program products, please note the following differences and guidelines: wp# pin has replaced du (don?t use) pin #12 in the 40-lead tsop package. in the 44-lead psop, du pin #2 is replaced with a 18 (see figure 1 and section 3.4 for details). connect the wp# pin to control signal or to v cc or gnd (in this case, a logic-level signal can be placed on du pin #12 for 40- lead tsop). see tables 2 and 9 to see how the wp# pin works. 5v program/erase operation has been added. if switching v pp for write protection, switch to gnd (not 5v) for complete write protection. to take advantage of 5v write-capability, allow for connecting 5v to v pp and disconnecting 12v from v pp line. enhanced circuits optimize low v cc performance, allowing operation down to v cc = 2.7v (using the be/ce products). to upgrade from lower density smartvoltage boot block products, the similar pinouts in the 40-lead and 48-lead tsop packages provide easy upgrades by adding extra address lines (see figures 1 and 3 ). in the 44-lead tsop, the wp# pin on the 2-mbit and 4-mbit bv parts becomes a 18 , removing the capability to unlock the boot block with a logic-level signal in this package only . the boot block can still be unlocked with 12v on rp# (see figure 2 and section 3.4 for details).
8-mbit smartvoltage boot block flash memory family e 4 product preview table 1 . smartvoltage provides total voltage flexibility product bus v cc v pp name width 2.7?3.6v 3.3 0.3v 5v 5% 5v 10% 5 10%v 12 5%v 28f008bv- t/b x8 ? ? ? ? ? ? ? ? 28f800bv- t/b x8 or x16 ? ? ? ? ? ? ? ? 28f800cv- t/b x8 or x16 ? ? ? ? ? ? ? ? 28f008be- t/b x8 ? ? ? ? ? ? ? ? 28f800ce- t/b x8 or x16 ? ? ? ? ? ? ? ?
e 8-mbit smartvoltage boot block flash memory family 5 product preview 1.2 main features intel?s smartvoltage technology is the most flexible voltage solution in the flash industry, providing two discrete voltage supply pins: v cc for read operation, and v pp for program and erase operation. discrete supply pins allow system designers to use the optimal voltage levels for their design. all products (28f800bv/cv, 28f008bv, 28f800ce and 28f008be) provide program/erase capability at 5v or 12v. the 28f800bv/cv and 28f008bv allows reads with v cc at 3.3 0.3v or 5v, while the 28f800ce and 28f008be allows reads with v cc at 2.7?3.6v or 5v. since many designs read from the flash memory a large percentage of the time, 2.7v v cc operation can provide great power savings. if read performance is an issue, however, 5v v cc provides faster read access times. for program and erase operations, 5v v pp operation eliminates the need for in system voltage converters, while 12v v pp operation provides faster program and erase for situations where 12v is available, such as manufacturing or designs where 12v is in- system. for design simplicity, however, just hook up v cc and v pp to the same 5v 10% source. the 28f800/28f008b boot block flash memory family is a high-performance, 8 -mbit (8,388,608 bit) flash memory family organized as either 512 kwords of 16 bits each (28f800 only) or 1024 kbytes of 8 bits each (28f800 and 28f008b). separately erasable blocks, including a hardware-lockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each) and main blocks (one block of 98,304 bytes and seven blocks of 131,072 bytes) define the boot block flash family architecture. see figures 4 and 5 for memory maps. each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. the boot block is located at either the top (denoted by -t suffix) or the bottom ( -b suffix) of the address map in order to accommodate different microprocessor protocols for boot code location. the hardware-lockable boot block provides complete code security for the kernel code required for system initialization. locking and unlocking of the boot block is controlled by wp# and/or rp# (see section 3.4 for details).
8-mbit smartvoltage boot block flash memory family e 6 product preview the command user interface (cui) serves as the interface between the microprocessor or microcontroller and the internal operation of the boot block flash memory products. the internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller of these tasks. the status register (sr) indicates the status of the wsm and whether it successfully completed the desired program or erase operation. program and erase automation allows program and erase operations to be executed using an industry-standard two- write command sequence to the cui. data writes are performed in word (28f800 family) or byte (28f800 or 28f008b families) increments. each byte or word in the flash memory can be programmed independently of other memory locations, unlike erases, which erase all locations within a block simultaneously. the 8 -mbit smartvoltage boot block flash memory family is also designed with an automatic power savings (aps) feature which minimizes system battery current drain, allowing for very low power designs. to provide even greater power savings, the boot block family includes a deep power- down mode which minimizes power consumption by turning most of the flash memory?s circuitry off. this mode is controlled by the rp# pin and its usage is discussed in section 3.5, along with other power consumption issues. additionally, the rp# pin provides protection against unwanted command writes due to invalid system bus conditions that may occur during system reset and power-up/down sequences. for example, when the flash memory powers-up, it automatically defaults to the read array mode, but during a warm system reset, where power continues uninterrupted to the system components, the flash memory could remain in a non-read mode, such as erase. consequently, the system reset signal should be tied to rp# to reset the memory to normal read mode upon activation of the reset signal (see section 3.6). the 28f800 provides both byte-wide or word-wide input/output, which is controlled by the byte# pin. please see table 2 and figure 13 for a detailed description of byte# operations, especially the usage of the dq 15 /a ?1 pin.
e 8-mbit smartvoltage boot block flash memory family 7 product preview the 28f800 products are available in the 44-lead psop (plastic small outline) package (a rom/eprom-compatible pinout) and the 48-lead tsop (thin small outline, 1.2 mm thick) package as shown in figures 2 , and 3 , respectively. the 28f800 is not available in 56-lead tsop. the 28f008b products are available in the 40- lead tsop package as shown in figure 1 . refer to the dc characteristics table, section 5.2 (commercial temperature) and section 6.2 (extended temperature), for complete current and voltage specifications. refer to the ac characteristics table, section 5.3 (commercial temperature) and section 6.3 (extended temperature), for read, write and erase performance specifications. 1.3 applications the 8 -mbit boot block flash memory family combines high-density, low-power, high- performance, cost-effective flash memories with blocking and hardware protection capabilities. their flexibility and versatility reduce costs throughout the product life cycle. flash memory is ideal for just-in- time production flow, reducing system inventory and costs, and eliminating component handling during the production phase. when your product is in the end-user?s hands, and updates or feature enhancements become necessary, flash memory reduces the update costs by allowing user- performed code changes instead of costly product returns or technician calls. the 8 -mbit boot block flash memory family provides full-function, blocked flash memories suitable for a wide range of applications. these applications include rom-able applications storage, digital cellular phone program and data storage, telecommunication boot/firmware, printer firmware/font storage and various other embedded applications where program and data storage are required. the 8 -mbit flash memory products are also excellent design solutions for digital cellular phone and telecommunication switching applications requiring very low power consumption, high-performance, high-density storage capability, modular software designs, and a small form factor package. the 8 -mbit?s blocking scheme allows for easy segmentation of the embedded code with 16 kbytes of hardware-protected boot code, eight main blocks of program code and two parameter blocks of 8 kbytes each for frequently updated data storage and diagnostic messages (e.g., phone numbers, authorization codes). intel?s boot block architecture provides a flexible solution for the different design needs of various applications. the asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. the boot block provides a secure boot prom; the parameter blocks can emulate eeprom functionality for parameter store with proper software techniques; and the main blocks provide code and data storage with access times fast enough to execute code in place, decreasing ram requirements.
8-mbit smartvoltage boot block flash memory family e 8 product preview 1.4 pinouts intel?s smartvoltage boot block architecture provides pinout upgrade paths to the 8 -mbit density. 8 -mbit pinouts are given on the chip illustration in the center, with 2-mbit and 4-mbit pinouts going outward from the center for reference. the 28f008b 40-lead tsop pinout for space-constrained designs is shown in figure 1 . for designs that require x16 operation but have space concerns, refer to the 48-lead pinout in figure 3 . the 28f800 44-lead psop pinout follows the industry- standard rom/eprom pinout, as shown in figure 2 . 2 8 f 0 0 8 b 4 0 - l e a d t s o p b o o t b l o c k 1 0 m m x 2 0 m m t o p v i e w 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 2 0 1 9 1 7 1 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 6 1 5 a 1 a 2 a 3 r p # w e # v p p a 1 6 a 1 5 a 7 a 6 a 5 a 4 a 1 4 a 1 3 a 8 a 9 a 1 1 a 1 2 w p # n c 2 8 f 0 0 4 b 2 8 f 0 0 4 b a 1 a 2 a 3 r p # w e # v p p a 1 6 a 1 5 a 7 a 6 a 5 a 4 a 1 4 a 1 3 a 8 a 9 a 1 1 a 1 2 w p # a 1 8 d q 7 c e # o e # g n d a 0 d q 6 d q 5 d q 4 d q 2 d q 1 d q 0 v c c d q 3 a 1 7 g n d n c a 1 0 n c n c v c c d q 7 c e # o e # g n d a 0 d q 6 d q 5 d q 4 d q 2 d q 1 d q 0 v c c d q 3 a 1 7 g n d n c a 1 0 n c n c v c c 2 8 f 0 0 2 b 2 8 f 0 0 2 b a 1 a 2 a 3 r p # w e # v p p a 1 6 a 1 5 a 7 a 6 a 5 a 4 a 1 4 a 1 3 a 8 a 9 a 1 1 a 1 2 w p # a 1 8 d q 7 c e # o e # g n d a 0 d q 6 d q 5 d q 4 d q 2 d q 1 d q 0 v c c d q 3 a 1 7 g n d n c a 1 0 n c v c c a 1 9 0539_01 note: 1. pin 12 is du for -bx/bl 12v v pp versions. 2. the 28f008b pinout is for the 8 -mbit boot block and not for the 28f008sa flashfile? memory. figure 1 . the 40-lead tsop offers the smallest form factor for space-constrained applications
e 8-mbit smartvoltage boot block flash memory family 9 product preview c e # g n d o e # a 7 a 5 a 6 a 4 a 3 a 2 a 1 a 0 d q 0 d q 8 d q 1 d q 9 d q 2 d q 1 0 d q 3 d q 1 1 v p p a 1 7 a 1 8 c e # w p # g n d o e # a 7 a 5 a 6 a 4 a 3 a 2 a 1 a 0 d q 0 d q 8 d q 1 d q 9 d q 2 d q 1 0 d q 3 d q 1 1 v p p a 1 7 p a 2 8 f 8 0 0 b o o t b l o c k 4 4 - l e a d p s o p 0 . 5 2 5 " x 1 . 1 1 0 " t o p v i e w g n d w e # r p # b y t e # a 8 a 9 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 d q 7 d q 1 4 d q 6 d q 1 3 d q 1 2 d q 4 v c c d q 5 a 1 0 a 1 5 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 2 2 2 1 2 0 1 9 1 7 1 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 6 1 5 n c c e # w p # g n d o e # a 7 a 5 a 6 a 4 a 3 a 2 a 1 a 0 d q 0 d q 8 d q 1 d q 9 d q 2 d q 1 0 d q 3 d q 1 1 v p p g n d w e # r p # b y t e # a 8 a 9 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 d q 7 d q 1 4 d q 6 d q 1 3 d q 1 2 d q 4 v c c d q 5 a 1 0 a 1 5 2 8 f 2 0 0 2 8 f 2 0 0 d q 1 5 - 1 / a d q 1 5 - 1 / a 2 8 f 4 0 0 g n d w e # r p # b y t e # a 8 a 9 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 d q 7 d q 1 4 d q 6 d q 1 3 d q 1 2 d q 4 v c c d q 5 a 1 0 a 1 5 2 8 f 4 0 0 d q 1 5 - 1 / a 0539_02 note: pin 2 is du for bx/bl 12v v pp versions, but for the 8 - mbit device, pin 2 has been changed to a 18 (wp# on 2/4 mbit). designs planning on upgrading to the 8 -mbit density from the 2/4-mbit density in this package should design pin 2 to control wp# functionality at the 2/4-mbit level and allow for pin 2 to control a 18 after upgrading to the 8 -mbit density. figure 2 . the 44-lead psop offers a convenient upgrade from jedec rom standards 2 8 f 8 0 0 c b o o t b l o c k 4 8 - l e a d t s o p 1 2 m m x 2 0 m m t o p v i e w 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 2 4 2 3 2 2 2 1 2 0 1 9 1 7 1 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 6 1 5 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 a 1 a 2 a 3 r p # w e # a 1 5 a 7 a 6 a 5 a 4 a 1 4 a 1 3 a 8 a 9 a 1 1 a 1 2 v p p n c n c n c a 1 0 w p # n c c e # o e # g n d a 0 v c c g n d b y t e # a 1 6 d q 1 5 / a - 1 d q 7 d q 1 4 d q 6 d q 1 3 d q 5 d q 1 2 d q 4 d q 1 1 d q 1 0 d q 2 d q 9 d q 1 d q 8 d q 0 d q 3 a 1 a 2 a 3 r p # w e # a 1 5 a 7 a 6 a 5 a 4 a 1 4 a 1 3 a 8 a 9 a 1 1 a 1 2 v p p n c n c n c a 1 7 a 1 0 w p # c e # o e # g n d a 0 v c c g n d b y t e # a 1 6 d q 1 5 / a - 1 d q 7 d q 1 4 d q 6 d q 1 3 d q 5 d q 1 2 d q 4 d q 1 1 d q 1 0 d q 2 d q 9 d q 1 d q 8 d q 0 d q 3 c e # o e # g n d a 0 v c c g n d b y t e # a 1 6 d q 1 5 / a - 1 d q 7 d q 1 4 d q 6 d q 1 3 d q 5 d q 1 2 d q 4 d q 1 1 d q 1 0 d q 2 d q 9 d q 1 d q 8 d q 0 d q 3 2 8 f 2 0 0 2 8 f 4 0 0 2 8 f 2 0 0 2 8 f 4 0 0 n c a 1 8 a 1 a 2 a 3 r p # w e # a 1 5 a 7 a 6 a 5 a 4 a 1 4 a 1 3 a 8 a 9 a 1 1 a 1 2 v p p n c n c n c a 1 0 w p # n c a 1 7 0539_03 figure 3 . the 48-lead tsop offers the smallest form factor for x16 operation
8-mbit smartvoltage boot block flash memory family e 10 product preview 1.5 pin descriptions table 2 . 28f800/008b pin descriptions symbol type name and function a 0 ?a 19 input address inputs for memory addresses. addresses are internally latched during a write cycle. the 28f800 only has a 0 ?a 18 pins, while the 28f008b has a 0 ?a 19 . a 9 input address input: when a 9 is at v hh the signature mode is accessed. during this mode, a 0 decodes between the manufacturer and device ids. when byte# is at a logic low, only the lower byte of the signatures are read. dq 15 /a ?1 is a don?t care in the signature mode when byte# is low. dq 0 ? dq 7 input/out put data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. inputs commands to the command user interface when ce# and we# are active. data is internally latched during the write cycle. outputs array, intelligent identifier and status register data. the data pins float to tri-state when the chip is de- selected or the outputs are disabled. dq 8 ? dq 15 input/out put data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. data is internally latched during the write cycle. outputs array data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled as in the byte-wide mode (byte# = ?0?). in the byte-wide mode dq 15 /a ?1 becomes the lowest order address for data output on dq 0 ?dq 7 . the 28f008b does not include these dq 8 ?dq 15 pins. ce# input chip enable: activates the device?s control logic, input buffers, decoders and sense amplifiers. ce# is active low. ce# high de-selects the memory device and reduces power consumption to standby levels. if ce# and rp# are high, but not at a cmos high level, the standby current will increase due to current flow through the ce# and rp# input stages. oe# input output enable: enables the device?s outputs through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the command register and array blocks. we# is active low. addresses and data are latched on the rising edge of the we# pulse.
e 8-mbit smartvoltage boot block flash memory family 11 product preview rp# input reset/deep power-down: uses three voltage levels (v il , v ih , and v hh ) to control two different functions: reset/deep power-down mode and boot block unlocking. it is backwards-compatible with the bx/bl/bv products. when rp# is at logic low, the device is in reset/deep power-down mode , which puts the outputs at high-z, resets the write state machine, and draws minimum current. when rp# is at logic high, the device is in standard operation . when rp# transitions from logic-low to logic- high, the device defaults to the read array mode. when rp# is at v hh , the boot block is unlocked and can be programmed or erased. this overrides any control from the wp# input.
8-mbit smartvoltage boot block flash memory family e 12 product preview table 2 . 28f800/008b pin descriptions (continued) symbol type name and function wp# input write protect: provides a method for unlocking the boot block in a system without a 12v supply. when wp# is at logic low, the boot block is locked , preventing program and erase operations to the boot block. if a program or erase operation is attempted on the boot block when wp# is low, the corresponding status bit (bit 4 for program, bit 5 for erase) will be set in the status register to indicate the operation failed. when wp# is at logic high, the boot block is unlocked and can be programmed or erased. note: this feature is overridden and the boot block unlocked when rp# is at v hh . this pin is not available on the 44-lead psop package. see section 3.4 for details on write protection. byte# input byte# enable: not available on 28f008b . controls whether the device operates in the byte-wide mode (x8) or the word-wide mode (x16). byte# pin must be controlled at cmos levels to meet the cmos current specification in the standby mode. when byte# is at logic low, the byte-wide mode is enabled , where data is read and programmed on dq 0 ?dq 7 and dq 15 /a ?1 becomes the lowest order address that decodes between the upper and lower byte. dq 8 ?dq 14 are tri-stated during the byte-wide mode. when byte# is at logic high, the word-wide mode is enabled , where data is read and programmed on dq 0 ?dq 15 . v cc device power supply: 5.0v 10%, 3.3v 0.3v, 2.7v?3.6v v pp program/erase power supply: for erasing memory array blocks or programming data in each block, a voltage either of 5v 10% or 12v 5% must be applied to this pin. when v pp < v pplk all blocks are locked and protected against program and erase commands. gnd ground: for all internal circuitry.
e 8-mbit smartvoltage boot block flash memory family 13 product preview nc no connect: pin may be driven or left floating. 2. 0 product description 2.1 memory organization 2.1.1 blocking this product family features an asymmetrically- blocked architecture providing system memory integration. each erase block can be erased independently of the others up to 100,000 times for commercial temperature or up to 10,000 times for extended temperature. the block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. the combination of block sizes in the boot block architecture allow the integration of several memories into a single chip. for the address locations of the blocks, see the memory maps in figures 4 and 5. 2.1.1.1 boot block - 1 x 16 kb the boot block is intended to replace a dedicated boot prom in a microprocessor or microcontroller-based system. the 16- kbyte (16,384 bytes) boot block is located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map to accommodate different microprocessor protocols for boot code location. this boot block features hardware controllable write- protection to protect the crucial microprocessor boot code from accidental modification. the protection of the boot block is controlled using a combination of the v pp , rp#, and wp# pins, as is detailed in section 3.4. 2.1.1.2 parameter blocks - 2 x 8 kb the boot block architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would normally require an eeprom. by using software techniques, the byte-rewrite functionality of eeproms can be emulated. these techniques are detailed in intel?s ap-604,
8-mbit smartvoltage boot block flash memory family e 14 product preview ?using intel?s boot block flash memory parameter blocks to replace eeprom.? each boot block component contains two parameter blocks of 8 kbytes (8,192 bytes) each. the parameter blocks are not write-protectable. 2.1.1.3 main blocks - 1 x 96 kb + 7 x 128 kb after the allocation of address space to the boot and parameter blocks, the remainder is divided into main blocks for data or code storage. each 8 -mbit device contains one 96-kbyte (98,304 byte) block and seven 128-kbyte (131,072 byte) blocks. see the memory maps for each device for more information. 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 7ffffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 04000h 03fffh 03000h 02fffh 02000h 01fffh 00000h 28f800-b 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 00000h 0ffffh 10000h 1ffffh 20000h 2ffffh 30000h 3ffffh 40000h 4ffffh 50000h 5ffffh 60000h 6ffffh 70000h 7bfffh 7c000h 7cfffh 7d000h 7dfffh 7e000h 7ffffh 28f800-t 0539_04 note: in x8 operation, the least significant system address should be connected to a ?1 . memory maps are shown for x16 operation. figure 4 . word-wide x16-mode memory maps
e 8-mbit smartvoltage boot block flash memory family 15 product preview 28f800-t 28f800-b 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 00000h 1ffffh 20000h 3ffffh 40000h 5ffffh 60000h 7ffffh 80000h 9ffffh a0000h bffffh c0000h dffffh e0000h f7fffh f8000h f9fffh fa000h fbfffh fc000h fffffh 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block 128-kbyte main block fffffh e0000h dffffh c0000h bffffh a0000h 9ffffh 80000h 7ffffh 60000h 5ffffh 40000h 3ffffh 20000h 1ffffh 08000h 07fffh 06000h 05fffh 04000h 03fffh 00000h 0539_05 note: these memory maps apply to the 28f008b or the 28f800 (in x8 mode). figure 5 . byte-wide x8-mode memory maps
8-mbit smartvoltage boot block flash memory family e 16 product preview 3. 0 product family principles of operation flash memory combines eprom functionality with in-circuit electrical write and erase. the boot block flash family utilizes a command user interface (cui) and automated algorithms to simplify write and erase operations. the cui allows for 100% ttl-level control inputs, fixed power supplies during erasure and programming, and maximum eprom compatibility. when v pp < v pplk , the device will only successfully execute the following commands: read array, read status register, clear status register and intelligent identifier mode. the device provides standard eprom read, standby and output disable operations. manufacturer identification and device identification data can be accessed through the cui or through the standard eprom a 9 high voltage access (v id ) for prom programming equipment. the same eprom read, standby and output disable functions are available when 5v or 12v is applied to the v pp pin. in addition, 5v or 12v on v pp allows write and erase of the device. all functions associated with altering memory contents: program and erase, intelligent identifier read, and read status are accessed via the cui. the internal write state machine (wsm) completely automates program and erase, beginning operation signaled by the cui and reporting status through the status register. the cui handles the we# interface to the data and address latches, as well as system status requests during wsm operation. 3.1 bus operations flash memory reads, erases and writes in- system via the local cpu. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. these bus operations are summarized in tables 3 and 4. 3.2 read operations 3.2.1 read array when rp# transitions from v il (reset) to v ih , the device will be in the read array mode and will respond to the read control inputs (ce#, address inputs, and oe#) without any commands being written to the cui. when the device is in the read array mode, five control signals must be controlled to obtain data at the outputs. we# must be logic high (v ih ) ce# must be logic low (v il ) oe must be logic low (v il ) rp# must be logic high (v ih ) byte# must be logic high or logic low. in addition, the address of the desired location must be applied to the address pins. refer to figures 12 and 13 for the exact sequence and timing of these signals. if the device is not in read array mode, as would be the case after a program or erase operation, the read mode command (ffh) must be written to the cui before reads can take place.
e 8-mbit smartvoltage boot block flash memory family 17 product preview table 3 . bus operations for word-wide mode (byte# = v ih ) mode note s rp# ce# oe# we# a 9 a 0 v pp dq 0?15 read 1,2,3 v ih v il v il v ih x x x d out output disable v ih v il v ih v ih x x x high z standby v ih v ih x x x x x high z deep power- down 9 v il x x x x x x high z intelligent identifier (mfr.) 4 v ih v il v il v ih v id v il x 0089 h intelligent identifier (device) 4,5 v ih v il v il v ih v id v ih x see table 5 write 6,7,8 v ih v il v ih v il x x x d in
8-mbit smartvoltage boot block flash memory family e 18 product preview table 4 . bus operations for byte-wide mode (byte# = v il ) mode note s rp# ce# oe # we # a 9 a 0 a ?1 v pp dq 0?7 dq 8? 14 read 1,2,3 v ih v il v il v ih x x x x d out high z output disable v ih v il v ih v ih x x x x high z high z standby v ih v ih x x x x x x high z high z deep power- down 9 v il x x x x x x x high z high z intelligent identifier (mfr.) 4 v ih v il v il v ih v id v il x x 89h high z intelligent identifier (device) 4,5 v ih v il v il v ih v id v ih x x see table 6 high z write 6,7,8 v ih v il v ih v il x x x x d in high z notes: 1. refer to dc characteristics. 2. x can be v il , v ih for control pins and addresses, v pplk or v pph for v pp . 3. see dc character istics for v pplk , v pph 1, v pph 2, v hh , v id voltages 4. manufacturer and device codes may also be accessed via a cui write sequence, a 1 ?a 18 = x, a 1 ?a 19 = x. 5. see table 5 for device ids. 6. refer to table 7 for valid d in during a write operation. 7. command writes for block erase or word/byte write are only executed when v pp = v pph 1 or v pph 2. 8. to write or erase the boot block, hold rp# at v hh or wp# at v ih . see section 3.4. 9. rp# must be at gnd 0.2v to meet the maximum deep power-down current specified.
e 8-mbit smartvoltage boot block flash memory family 19 product preview 3.2.2 intelligent identifiers to read the manufacturer and device codes, the device must be in intelligent identifier read mode, which can be reached using two methods: by writing the intelligent identifier command (90h) or by taking the a 9 pin to v id . once in intelligent identifier read mode, a 0 = 0 outputs the manufacturer?s identification code and a 0 = 1 outputs the device code. in byte-wide mode, only the lower byte of the above signatures is read (dq 15 /a ?1 is a ?don?t care? in this mode). see table 5 for product signatures. to return to read array mode, write a read array command (ffh). table 5 . intelligent identifier table produc t mfr. id device id -t (top boot) -b (bottom boot) 28f800 0089 h 889c h 889d h 28f008 b 89 h 9c h 9d h 3.3 write operations 3.3.1 command user interface (cui) the command user interface (cui) is the interface between the microprocessor and the internal chip controller. commands are written to the cui using standard microprocessor write timings. the available commands are read array, read intelligent identifier, read status register, clear status register, erase and program (summarized in tables 6 and 7 ). the three read modes are read array, intelligent identifier read, and status register read. for program or erase commands, the cui informs the write state machine (wsm) that a write or erase has been requested. during the execution of a program command, the wsm will control the programming sequences and the cui will only respond to status reads. during an erase cycle, the cui will respond to status reads and erase suspend. after the wsm has completed its task, it will set the wsm status bit to a ?1? (ready), which indicates that the cui can respond to its full command set. note that after the wsm has returned control to the cui, the cui will stay in the current command state until it receives another command. 3.3.1.1 command function description device operations are selected by writing specific commands into the cui. tables 6 and 7 define the available commands.
8-mbit smartvoltage boot block flash memory family e 20 product preview table 6 . command codes and descriptions code device mode description 00 invalid/ reserved unassigned commands that should not be used. intel reserves the right to redefine these codes for future functions. ff read array/ program or erase abort places the device in read array mode, so that array data will be output on the data pins. this command can also be used to cancel erase and program sequences after their set-up commands have been issued. to cancel after issuing an erase set-up command, issue this command, which will reset to read array mode. to cancel a program operation after issuing a program set-up command, issue two read array commands in sequence to reset to read array mode. if a program or erase operation has already been initiated to the wsm this command can not cancel that operation in progress. 40 program set-up sets the cui into a state such that the next write will load the address and data registers. after this command is executed, the outputs default to the status register. a two read array command sequence (ffh) is required to reset to read array after the program set-up command. the second write after the program set-up command will latch addresses and data, initiating the wsm to begin execution of the program algorithm. the device outputs status register data when oe# is enabled. a read array command is required after programming, to read array data. see section 3.3.3. 10 alternate program set- up (see 40h/program set-up) 20 erase set-up prepares the cui for the erase confirm command. if the next command is not an erase confirm command, then the cui will set both the program status and erase status bits of the status register to a ?1,? place the device into the read status register state, and wait for another command. see section 3.3.4. d0 erase resume/ erase confirm if the previous command was an erase set-up command, then the cui will close the address and data latches, and begin erasing the block indicated on the address pins. during erase, the device will respond only to the read status register and erase suspend commands and will output status register data when oe# is toggled low. status register data can be updated by toggling either
e 8-mbit smartvoltage boot block flash memory family 21 product preview table 6 . command codes and descriptions code device mode description oe# or ce# low. b0 erase suspend valid only while an erase operation is in progress and will be ignored in any other circumstance. issuing this command will begin to suspend erase operation. the status register will indicate when the device reaches erase suspend mode. in this mode, the cui will respond only to the read array, read status register, and erase resume commands and the wsm will also set the wsm status bit to a ?1? (ready). the wsm will continue to idle in the suspend state, regardless of the state of all input control pins except rp#, which will immediately shut down the wsm and the remainder of the chip, if it is made active. during a suspend operation, the data and address latches will remain closed, but the address pads are able to drive the address into the read path. see section 3.3.4.1. 70 read status register puts the device into the read status register mode, so that reading the device will output the contents of the status register, regardless of the address presented to the device. the device automatically enters this mode after program or erase has completed. this is one of the two commands that is executable while the wsm is operating. see section 3.3.2.
8-mbit smartvoltage boot block flash memory family e 22 product preview table 6 . command codes and descriptions (continued) code device mode description 50 clear status register the wsm can only set the program status and erase status bits in the status register to ?1,? it cannot clear them to ?0.? the status register operates in this fashion for two reasons. the first is to give the host cpu the flexibility to read the status bits at any time. second, when programming a string of bytes, a single status register query after programming the string may be more efficient, since it will return the accumulated error status of the entire string. see section 3.3.2.1. 90 intelligent identifier puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes. (a 0 = 0 for manufacturer, a 0 = 1 for device, all other address inputs are ignored). see section 3.2.2. table 7 . command bus definitions first bus cycle second bus cycle command note oper addr data oper addr data read array 8 write x ffh intelligent identifier 1 write x 90h read ia iid read status register 2,4 write x 70h read x srd clear status register 3 write x 50h word/byte write write wa 40h write wa wd alternate word/byte write 6,7 write wa 10h write wa wd block erase/confirm 6,7 write ba 20h write ba d0h erase suspend/resume 5 write x b0h write x d0h address data ba= block address srd= status register data ia= identifier address iid= identifier data wa= write address wd= write data x= don?t care notes:
e 8-mbit smartvoltage boot block flash memory family 23 product preview 1. bus operations are defined in tables 3 and 4. 2. ia = identifier address: a 0 = 0 for manufacturer code, a 0 = 1 for device code. 3. srd - data read from status register. 4. iid = intelligent identifier data. following the intelligent identifier command, two read operations access manufacturer and device codes. 5. ba = addre ss within the block being erased. 6. wa = address to be written. wd = data to be written at location wd. 7. either 40h or 10h commands is valid. 8. when writing commands to the device, the upper data bus [dq 8 ?dq 15 ] = x (28f800 only) which is either v il or v ih , to minimize current draw.
8-mbit smartvoltage boot block flash memory family e 24 product preview table 8 . status register bit definition wsms ess es dws vpps r r r 7 6 5 4 3 2 1 0 notes: sr.7 write state machine status 1 = ready (wsms) 0 = busy check write state machine bit first to determine word/byte program or block erase completion, before checking program or erase status bits. sr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to ?1.? ess bit remains set to ?1? until an erase resume command is issued. sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase when this bit is set to ?1,? wsm has applied the max number of erase pulses to the block and is still unable to verify successful block erasure. sr.4 = program status (dws) 1 = error in byte/word program 0 = successful byte/word program when this bit is set to ?1,? wsm has attempted but failed to program a byte or word. sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok the v pp status bit does not provide continuous indication of v pp level. the wsm interrogates v pp level only after the byte write or erase command sequences have been entered, and informs the system if v pp has not been switched on. the v pp status bit is not guaranteed to report accurate feedback between v pplk and v pph . sr.2-sr.0 = reserved for future enhancements (r) these bits are reserved for future use and should be masked out when polling the status register. 3.3.2 status register the device status register indicates when a program or erase operation is complete, and the success or failure of that operation. to read the status register write the read status (70h) command to the cui. this causes all subsequent read operations to output data from the status register until another command is written to the cui. to return to reading from the array, issue a read array (ffh) command.
e 8-mbit smartvoltage boot block flash memory family 25 product preview the status register bits are output on dq 0 ? dq 7 , in both byte-wide (x8) or word-wide (x16) mode. in the word-wide mode the upper byte, dq 8 ?dq 15 , outputs 00h during a read status command. in the byte-wide mode, dq 8 ?dq 14 are tri-stated and dq 15 /a ? 1 retains the low order address function. important: the contents of the status register are latched on the falling edge of oe# or ce#, whichever occurs last in the read cycle. this prevents possible bus errors which might occur if status register contents change while being read. ce# or oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. when the wsm is active, the sr.7 register will indicate the status of the wsm, and will also hold the bits indicating whether or not the wsm was successful in performing the desired operation. 3.3.2.1 clearing the status register the wsm sets status bits 3 through 7 to ?1,? and clears bits 6 and 7 to ?0,? but cannot clear status bits 3 through 5 to ?0.? bits 3 through 5 can only be
8-mbit smartvoltage boot block flash memory family e 26 product preview cleared by the controlling cpu through the use of the clear status register (50h) command, because these bits indicate various error conditions. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning another command or sequence. note, again, that a read array command must be issued before data can be read from the memory or intelligent identifier. 3.3.3 program mode programming is executed using a two-write sequence. the program setup command is written to the cui followed by a second write which specifies the address and data to be programmed. the wsm will execute a sequence of internally timed events to: 1. program the desired bits of the addressed memory word or byte. 2. verify that the desired bits are sufficiently programmed. programming of the memory results in specific bits within a byte or word being changed to a ?0.? if the user attempts to program ?1?s, there will be no change of the memory cell content and no error occurs. the status register indicates programming status: while the program sequence is executing, bit 7 of the status register is a ?0.? the status register can be polled by toggling either ce# or oe#. while programming, the only valid command is read status register. when programming is complete, the program status bits should be checked. if the programming operation was unsuccessful, bit 4 of the status register is set to a ?1? to indicate a program failure. if bit 3 is set to a ?1,? then v pp was not within acceptable limits, and the wsm did not execute the programming sequence.
e 8-mbit smartvoltage boot block flash memory family 27 product preview the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, reads from the memory array or intelligent identifier cannot be accomplished until the cui is given the appropriate command. 3.3.4 erase mode to erase a block, write the erase set-up and erase confirm commands to the cui, along with the addresses identifying the block to be erased. these addresses are latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to ?1.? only one block can be erased at a time. the wsm will execute a sequence of internally timed events to: 1. program all bits within the block to ?0.? 2. verify that all bits within the block are sufficiently programmed to ?0.? 3. erase all bits within the block to ?1.? 4. verify that all bits within the block are sufficiently erased. while the erase sequence is executing, bit 7 of the status register is a ?0.? when the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. if the erase operation was unsuccessful, bit 5 of the status register will be set to a ?1,? indicating an erase failure. if v pp was not within acceptable limits after the erase confirm command is issued, the wsm will not execute an erase sequence; instead, bit 5 of the status register is set to a ?1? to indicate an erase failure, and bit 3 is set to a ?1? to identify that v pp supply voltage was not within acceptable limits. clear the status register before attempting the next operation. any cui instruction can follow after erasure is completed; however, reads from the memory array, status register, or intelligent identifier cannot be accomplished until the cui is given the read array command.
8-mbit smartvoltage boot block flash memory family e 28 product preview 3.3.4.1 suspending and resuming erase since an erase operation requires on the order of seconds to complete, an erase suspend command is provided to allow erase-sequence interruption in order to read data from another block of the memory. once the erase sequence is started, writing the erase suspend command to the cui requests that the wsm pause the erase sequence at a predetermined point in the erase algorithm. the status register will indicate if/when the erase operation has been suspended. at this point, a read array command can be written to the cui in order to read data from blocks other than that which is being suspended. the only other valid command at this time is the erase resume command or read status register command. during erase suspend mode, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. to resume the erase operation, enable the chip by taking ce# to v il , then issuing the erase resume command, which continues the erase sequence to completion. as with the end of a standard erase operation, the status register must be read, cleared, and the next instruction issued in order to continue. 3.4 boot block lo cking the boot block family architecture features a hardware-lockable boot block so that the kernel code for the system can be kept secure while the parameter and main blocks are programmed and erased independently as necessary. only the boot block can be locked independently from the other blocks. 3.4.1 v pp = v il for complete protection for complete write protection of all blocks in the flash device, the v pp programming voltage can be held low. when v pp is below v pplk , any program or erase operation will result in a error in the status register.
e 8-mbit smartvoltage boot block flash memory family 29 product preview 3.4.2 wp# = v il for boot block locking when wp# = v il , the boot block is locked and any program or erase operation to the boot block will result in an error in the status register. all other blocks remain unlocked in this condition and can be programmed or erased normally. note that this feature is overridden and the boot block unlocked when rp# = v hh . since the wp# pin is not available on the 44-lead psop package, the boot block?s default status is locked when rp# is at v ih or v il . for the 44-lead psop, the boot block cannot be unlocked with a logic-level signal; instead, rp# must be taken to v hh as discussed in section 3.4.3 below. 3.4.3 rp# = v hh or wp# = v ih for boot block unlocking two methods can be used to unlock the boot block: 1. wp# = v ih 2. rp# = v hh if both or either of these two conditions are met, the boot block will be unlocked and can be programmed or erased. since the wp# pin is not available on the 44-lead psop package, the boot block cannot be unlocked with a logic-level signal on that package. instead, rp# must be taken to v hh . the truth table, table 9, clearly defines the write protection methods. table 9 . write protection truth table for smartvoltage boot block family v pp rp # wp # write protection provided v il x x all blocks locked 3 v pplk v il x all blocks locked (reset) 3 v pplk v hh x all blocks unlocked 3 v pplk v ih v il boot block locked 3 v pplk v ih v ih all blocks unlocked note: wp# pin not available on 44-lead psop. in this package, treat as if the wp# pin is internally tied low, effectively eliminating the last row of the above table.
8-mbit smartvoltage boot block flash memory family e 30 product preview s r . 7 = 1 ? n o y e s s t a r t w r i t e 4 0 h , w o r d / b y t e a d d r e s s w r i t e w o r d / b y t e d a t a / a d d r e s s f u l l s t a t u s c h e c k i f d e s i r e d w o r d / b y t e p r o g r a m c o m p l e t e f u l l s t a t u s c h e c k p r o c e d u r e 1 0 r e a d s t a t u s r e g i s t e r d a t a ( s e e a b o v e ) 1 0 r e a d s t a t u s r e g i s t e r v r a n g e e r r o r p p b u s o p e r a t i o n s t a n d b y s t a n d b y c h e c k s r . 3 1 = v l o w d e t e c t s r . 3 m u s t b e c l e a r e d , i f s e t d u r i n g a p r o g r a m a t t e m p t , b e f o r e f u r t h e r a t t e m p t s a r e a l l o w e d b y t h e w r i t e s t a t e m a c h i n e . s r . 4 i s o n l y c l e a r e d b y t h e c l e a r s t a t u s r e g i s t e r c o m m a n d , i n c a s e s w h e r e m u l t i p l e b y t e s a r e p r o g r a m m e d b e f o r e f u l l s t a t u s i s c h e c k e d . i f e r r o r i s d e t e c t e d , c l e a r t h e s t a t u s r e g i s t e r b e f o r e a t t e m p t i n g r e t r y o r o t h e r e r r o r r e c o v e r y . b u s o p e r a t i o n c o m m a n d c o m m e n t s w r i t e w r i t e s e t u p p r o g r a m d a t a = d a t a t o p r o g r a m a d d r = l o c a t i o n t o p r o g r a m r e a d d a t a = 4 0 h a d d r = w o r d / b y t e t o p r o g r a m c h e c k s r . 7 1 = w s m r e a d y 0 = w s m b u s y r e p e a t f o r s u b s e q u e n t w o r d / b y t e w r i t e s . s r f u l l s t a t u s c h e c k c a n b e d o n e a f t e r e a c h w o r d / b y t e w r i t e , o r a f t e r a s e q u e n c e o f w o r d / b y t e w r i t e s . w r i t e f f h a f t e r t h e l a s t w r i t e o p e r a t i o n t o r e s e t d e v i c e t o r e a d a r r a y m o d e . s t a n d b y s r . 3 = s r . 4 = w o r d / b y t e p r o g r a m e r r o r w o r d / b y t e p r o g r a m s u c c e s s f u l c h e c k s r . 4 1 = v b y t e p r o g r a m e r r o r p p p p p r o g r a m s t a t u s r e g i s t e r d a t a t o g g l e c e # o r o e # t o u p d a t e s r d . c o m m a n d c o m m e n t s 0539_06 figure 6 . automated word/byte programming flowchart
e 8-mbit smartvoltage boot block flash memory family 31 product preview s r . 7 = 0 1 s t a r t w r i t e 2 0 h , b l o c k a d d r e s s w r i t e d 0 h a n d b l o c k a d d r e s s f u l l s t a t u s c h e c k i f d e s i r e d b l o c k e r a s e c o m p l e t e f u l l s t a t u s c h e c k p r o c e d u r e 1 0 r e a d s t a t u s r e g i s t e r d a t a ( s e e a b o v e ) 1 0 r e a d s t a t u s r e g i s t e r v r a n g e e r r o r p p s u s p e n d e r a s e s u s p e n d e r a s e l o o p y e s n o 1 0 c o m m a n d s e q u e n c e e r r o r s r . 3 = s r . 5 = s r . 4 , 5 = b l o c k e r a s e e r r o r b u s o p e r a t i o n c o m m a n d c o m m e n t s s t a n d b y c h e c k s r . 4 , 5 b o t h 1 = c o m m a n d s e q u e n c e e r r o r s t a n d b y c h e c k s r . 3 1 = v l o w d e t e c t s r . 3 m u s t b e c l e a r e d , i f s e t d u r i n g a n e r a s e a t t e m p t , b e f o r e f u r t h e r a t t e m p t s a r e a l l o w e d b y t h e w r i t e s t a t e m a c h i n e . s r . 5 i s o n l y c l e a r e d b y t h e c l e a r s t a t u s r e g i s t e r c o m m a n d , i n c a s e s w h e r e m u l t i p l e b l o c k s a r e e r a s e b e f o r e f u l l s t a t u s i s c h e c k e d . i f e r r o r i s d e t e c t e d , c l e a r t h e s t a t u s r e g i s t e r b e f o r e a t t e m p t i n g r e t r y o r o t h e r e r r o r r e c o v e r y . c h e c k s r . 5 1 = b l o c k e r a s e e r r o r s t a n d b y b u s o p e r a t i o n c o m m a n d c o m m e n t s w r i t e w r i t e e r a s e s e t u p r e a d d a t a = 2 0 h a d d r = w i t h i n b l o c k t o b e e r a s e d c h e c k s r . 7 1 = w s m r e a d y 0 = w s m b u s y r e p e a t f o r s u b s e q u e n t b l o c k e r a s u r e s . f u l l s t a t u s c h e c k c a n b e d o n e a f t e r e a c h b l o c k e r a s e , o r a f t e r a s e q u e n c e o f b l o c k e r a s u r e s . w r i t e f f h a f t e r t h e l a s t o p e r a t i o n t o r e s e t d e v i c e t o r e a d a r r a y m o d e . s t a t u s r e g i s t e r d a t a t o g g l e c e # o r o e # t o u p d a t e s t a t u s r e g i s t e r s t a n d b y e r a s e c o n f i r m d a t a = d 0 h a d d r = w i t h i n b l o c k t o b e e r a s e d b l o c k e r a s e s u c c e s s f u l p p 0539_07 figure 7 . automated block erase flowchart
8-mbit smartvoltage boot block flash memory family e 32 product preview s r . 7 = 0 1 s t a r t w r i t e b 0 h r e a d s t a t u s r e g i s t e r w r i t e d 0 h e r a s e r e s u m e d b u s o p e r a t i o n c o m m a n d c o m m e n t s w r i t e e r a s e s u s p e n d r e a d d a t a = b 0 h a d d r = x c h e c k s r . 7 1 = w s m r e a d y 0 = w s m b u s y s t a t u s r e g i s t e r d a t a t o g g l e c e # o r o e # t o u p d a t e s r d . a d d r = x s t a n d b y c s r . 6 = w r i t e f f h r e a d a r r a y d a t a d o n e r e a d i n g e r a s e c o m p l e t e d w r i t e f f h r e a d a r r a y d a t a y e s n o 0 1 c h e c k s r . 6 1 = e r a s e s u s p e n d e d 0 = e r a s e c o m p l e t e d s t a n d b y d a t a = f f h a d d r = x w r i t e r e a d a r r a y d a t a f r o m b l o c k o t h e r t h a n t h e o n e b e i n g e r a s e d . r e a d d a t a = d 0 h a d d r = x w r i t e r e a d a r r a y e r a s e r e s u m e 0539_08 figure 8 . erase suspend/resume flowchart
e 8-mbit smartvoltage boot block flash memory family 33 product preview 3.5 power consumption 3.5.1 active power with ce# at a logic-low level and rp# at a logic-high level, the device is placed in the active mode. refer to the dc characteristics table for i cc current values. 3.5.2 automatic power savings (aps) automatic power savings (aps) provides low-power operation during active mode. power reduction control (prc) circuitry allows the device to put itself into a low current state when not being accessed. after data is read from the memory array, prc logic controls the device?s power consumption by entering the aps mode where typical i cc current is less than 1 ma. the device stays in this static state with outputs valid until a new location is read. 3.5.3 standby power with ce# at a logic-high level (v ih ), and the cui in read mode, the memory is placed in standby mode, which disables much of the device?s circuitry and substantially reduces power consumption. outputs (dq 0 ? dq 15 or dq 0 ?dq 7 ) are placed in a high- impedance state independent of the status of the oe# signal. when ce# is at logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. 3.5.4 deep power-down mode the smartvoltage boot block family supports a low typical i cc in deep power- down mode, which turns off all circuits to save power. this mode is activated by the rp# pin when it is at a logic-low (gnd 0.2v). note: byte# pin must be at cmos levels to meet the i ccd specification. during read modes, the rp# pin going low de-selects the memory and places the output drivers in a high impedance state. recovery from the deep power-down state, requires a minimum access time of t phqv (see ac characteristics table). during erase or program modes, rp# low will abort either erase or program operations, but the memory
8-mbit smartvoltage boot block flash memory family e 34 product preview contents are no longer valid as the data has been corrupted by the rp# function. as in the read mode above, all internal circuitry is turned off to achieve the power savings. rp# transitions to v il , or turning power off to the device will clear the status register. 3.6 power-up/down operation the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, v pp or v cc , powers- up first. the cui is reset to the read mode after power-up, but the system must drop ce# low or present a new address to ensure valid data at the outputs. a system designer must guard against spurious writes when v cc voltages are above v lko and v pp is active. since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (rp# connected to system powergood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.1 rp# connected to system reset the use of rp# during system reset is important with automated write/erase devices because the system expects to read from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization would not occur because the flash memory may be providing status information instead of array data. intel?s flash memories allow proper cpu initialization following a system reset by connecting the rp# pin to the same reset# signal that resets the system cpu. 3.6.2 v cc , v pp and rp# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from deep power-down mode, or after v cc transitions above v lko (lockout voltage), is read array mode. after any word/byte write or block erase operation is complete and even after v pp transitions down to v pplk , the cui must be reset to read array mode via the read array command if accesses to the flash memory are desired. please refer to ap-617, ?additional flash data protection using v pp , rp#, and wp#? for a circuit-level description of how to implement the protection discussed in section 3.6. 3.7 power supply decoupling flash memory?s power switching characteristics require careful device decoupling methods. system designers should consider three supply current issues: 1. standby curren t levels (i ccs ) 2. active current levels (i ccr ) 3. transient peaks produced by falling and rising edges of ce#.
e 8-mbit smartvoltage boot block flash memory family 35 product preview transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 v pp trace on printed circuit boards designing for in-system writes to the flash memory requires special consideration of the v pp power supply trace by the printed circuit board designer. the v pp pin supplies the flash memory cells current for programming and erasing. one should use similar trace widths and layout considerations given to the v cc power supply trace. adequate v pp supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. note: table headings in sections 5 and 6 (i.e., bv-70, bv-120, tbv-90, tbe-120) refer to the specific products listed below. see section 7.1 for more information on product naming and line items. abbreviatio n applicable product names bv-70 e28f008bv-t70, e28f008bv-b70, e28f800cv-t70, e28f800cv- b70, pa28f800bv-t70, pa28F800BV-B70 bv-120 e28f008bv-t120, e28f008bv-b120, pa28f800bv-t120, pa28F800BV-B120 tbv-90 te28f008bv-t90, te28f008bv-b90, te28f800cv-t90, te28f800cv-b90, tb28f800bv-t90, tb28F800BV-B90 tbe-120 te28f008be-t120, te28f008be-b120, te28f800ce-t120, te28f800ce-b120, tb28f800be-t120, tb28f800be-b120
8-mbit smartvoltage boot block flash memory family e 36 product preview 4. 0 absolute maximum ratings* commercial operating temperature during read ..................... 0c to +70c during block erase and word/byte write ....... 0c to +70c temperature bias ......... ?10c to +80c extended operating temperature during read ................. ?40c to +85c during block erase and word/byte write ... ?40c to +85c temperature under bias ?40c to +85c storage temperature ........ ?65c to +125c voltage on any pin (except v cc , v pp , a 9 and rp#) with respect to gnd . ?2.0v to +7.0v (2) voltage on pin rp# or pin a 9 with respect to gnd ?2.0v to +13.5v (2,3) v pp program voltage with respect to gnd during block erase and word/byte write ?2.0v to +14.0v (2,3) v cc supply voltage with respect to gnd . ?2.0v to +7.0v (2) output short circuit current ...... 100 ma (4) notice: this datasheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. operating temperature is fo r commercial product defined by this specification. 2. minimum dc voltage is ?0.5v on input/output pins. during transitions, this level may undershoot to ?2.0v for periods < 20 ns. maximum dc voltage on input/output pins is v cc + 0.5v which, during transitions, may overshoot to v cc + 2.0v for periods < 20 ns. 3. maximum dc voltage on v pp may overshoot to +14.0v for periods < 20 ns. maximum dc voltage on rp# or a 9 may overshoot to 13.5v for periods < 20 ns. 4. output shorted for no more than one second. n o more than one output shorted at a time.
e 8-mbit smartvoltage boot block flash memory family 37 product preview 5. 0 commercial operating conditions table 10 . commercial temperature and v cc operating conditions symbol parameter notes min max units t a operating temperature 0 +70 c v cc 3.3v v cc supply voltage ( 0.3v) 3.0 3.6 volts 5v v cc supply voltage (10%) 1 4.50 5.50 volts 5v v cc supply voltage (5%) 2 4.75 5.25 volts notes: 1. 10% v cc specifications apply to the 80 ns and 120 ns product versions in their standard test configuration. 2. 5% v cc specifications apply to the 80 ns versions in their high-speed test configuration. 5.1 applying v cc voltages when applying v cc voltage to the device, a delay may be required before initiating device operation, depending on the v cc ramp rate. if v cc ramps slower than 1v/100 s (0.01 v/s) then no delay is required. if v cc ramps faster than 1v/100 s (0.01 v/s), then a delay of 2 s is required before initiating device opeation. rp# = gnd is recommended during power- up to protect against spurious write signals when v cc is between v lko and v ccmin . v cc ramp rate required timing 1v/100 m s no delay required. > 1v/100 m s a delay time of 2 m s is required before any device operation is initiated, including read operations, command writes, program operations, and erase operations. this delay is measured beginning from the time v cc reaches v ccmin (3.0v for 3.3 0.3v operation; and 4.5v for 5v operation). notes: 1. these requirements must be strictly followed to guarantee all other read and write specifications. 2. to switch between 3.3v and 5v operation, the system should first transition v cc from the existing voltage range to gnd, and then to the new voltage. any time the v cc supply drops below v ccmin , the chip may be reset, aborting any operations pending or in progress. 3. these guidelines must be followed for any v cc transition from gnd.
8-mbit smartvoltage boot block flash memory family e 38 product preview 5.2 dc characteristics table 11. dc characteristics (commercial) prod bv-70 bv-120 sym parameter v cc 3.3 0.3v 5v 10% unit s test conditions note s typ max typ max i il input load current 1 1.0 1.0 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 10 a v cc = v cc max v in = v cc or gnd i ccs v cc standby current 1,3 0.4 1.5 0.8 2.0 ma v cc = v cc max ce# = rp# = byte# = wp# = v ih 60 110 50 130 a v cc = v cc max ce# = rp# = v cc 0.2v i ccd v cc deep power-down current 1 0.2 8 0.2 8 a v cc = v cc max v in = v cc or gnd rp# = gnd 0.2v i ccr v cc read current for word or byte 1,5,6 15 30 50 60 ma cmos inputs v cc = v cc max ce# = gnd, oe# = v cc f = 10 mhz (5v), 5 mhz (3.3v) i out = 0 ma inputs = gnd 0.2v or v cc 0.2v
e 8-mbit smartvoltage boot block flash memory family 39 product preview table 11. dc characteristics (commercial) 15 30 55 65 ma ttl inputs v cc = v cc max ce# = v il , oe# = v ih f = 10 mhz (5v), 5 mhz (3.3v) i out = 0 ma inputs = v il or v ih i ccw v cc write current for word or byte 1,4 13 30 30 50 ma v pp = v pph 1 (at 5v) word write in progress 10 25 30 45 ma v pp = v pph 2 (at 12v) word write in progress i cce v cc erase current 1,4 13 30 18 35 ma v pp = v pph 1 (at 5v) block erase in progress 10 25 18 30 ma v pp = v pph 2 (at 12v) block erase in progress i cces v cc erase suspend current 1,2 3 8.0 5 10 ma ce# = v ih block erase suspend
8-mbit smartvoltage boot block flash memory family e 40 product preview table 11. dc characteristics (commercial) (continued) prod bv-70 bv-120 sym parameter v cc 3.3 0.3v 5v 10% unit s test conditions note s typ max typ max i pps v pp standby current 1 0.5 15 0.5 10 a v pp < v pph 2 i ppd v pp deep power- down current 1 0.2 5 0.2 5.0 a rp# = gnd 0.2v i ppr v pp read current 1 50 200 30 200 a v pp 3 v pph 2 i ppw v pp word/byte current 1,4 13 30 13 25 ma v pp = v pph 1 (at 5v) word write in progress 8 25 8 20 v pp = v pph 2 (at 12v) word write in progress i ppe v pp erase current 1,4 13 30 10 20 ma v pp = v pph 1 (at 5v) block erase in progress 8 25 5 15 v pp = v pph 2 (at 12v) block erase in progress i ppes v pp erase suspend current 1 50 200 30 200 a v pp = v pph block erase suspend in progress i rp# rp# boot block unlock current 1,4 500 500 a rp# = v hh i id a 9 intelligent identifier current 1,4 500 500 a a 9 = v id
e 8-mbit smartvoltage boot block flash memory family 41 product preview table 11. dc characteristics (commercial) continued prod bv-70 bv-120 sym parameter v cc 3.3 0.3v 5v 10% unit test conditions notes min max min max v id a 9 intelligent identifier voltage 11.4 12.6 11.4 12.6 v v il input low voltage ?0.5 0.8 ?0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5v 2.0 v cc + 0.5v v v ol output low voltage 0.45 0.45 v v cc = v cc min i ol = 5.8 ma v oh 1 output high voltage (ttl) 2.4 2.4 v v cc = v cc min i oh = ?2.5 ma v oh 2 output high voltage (cmos) 0.85 x v cc 0.85 x v cc v v cc = v cc min i oh = ?2.5 ma v cc ? 0.4v v cc ? 0.4v v v cc = v cc min i oh = ?100 m a v ppl k v pp lock-out voltage 3 0.0 1.5 0.0 1.5 v complete write protection v pph 1 v pp (prog/erase operations) 4.5 5.5 4.5 5.5 v v pp at 5v v pph 2 v pp (prog/erase operations) 11.4 12.6 11.4 12.6 v v pp at 12v v lko v cc erase/write lock voltage 8 2.0 2.0 v
8-mbit smartvoltage boot block flash memory family e 42 product preview table 11. dc characteristics (commercial) continued v hh rp# unlock voltage 11.4 12.6 11.4 12.6 v boot block write/erase table 12. capacitance (t a = 25 c, f = 1 mhz) symbol parameter notes typ max units conditions c in input capacitance 4 6 8 pf v in = 0v c out output capacitance 4, 7 10 12 pf v out = 0v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0v, t = +25c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device deselected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases and word/byte writes are inhibit ed when v pp = v pplk , and not guaranteed in the range between v pph 1 and v pplk . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to less than 1 ma typical, in static operation. 6. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 7. for the 28f008b, address pin a 10 follows the c out capacitance numbers. 8. for all bv/cv parts, v lko = 2.0v for both 3.3v and 5v operations. test points input output 1 . 5 3 . 0 0 . 0 1 . 5 0539_09 note: ac test inputs are driven at 3.0v for a logic ?1? and 0.0v for a logic ?0.? input timing begins, and output timing ends, at 1.5v. input rise and fall times (10%?90%) <10 ns. figure 9 . 3.3v inputs and measurement points
e 8-mbit smartvoltage boot block flash memory family 43 product preview test points input output 2.0 0.8 0.8 2.0 2.4 0.45 0539_10 note: ac test inputs are driven at v oh (2.4 v ttl ) for a logic ?1? and v ol (0.45 v ttl ) for a logic ?0.? input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ) . output timing ends at v ih and v il . input rise and fall times (10%?90%) <10 ns. figure 10 . 5v inputs and measurement points c l o u t v c c d e v i c e u n d e r t e s t r 1 r 2 0539-11 note: see table for component values. figure 11 . test configuration test configuration component values test configuration c l (pf) r 1 ( w w ) r 2 ( w w ) 3.3v standard test 50 990 770 5v standard test 100 580 390 5v high-speed test 30 580 390 note: c l includes jig capacitance.
8-mbit smartvoltage boot block flash memory family e 44 product preview 5.3 ac characteristics table 13. ac characteristics: read only operations (commercial) prod bv-70 v cc 3.30.3v ( 5) 5v5% (6) 5v10% ( 7) symbo l parameter loa d 50 pf 30 pf 100 pf unit s note s min max min max min max t avav read cycle time 120 70 80 ns t avqv address to output delay 120 70 80 ns t elqv ce# to output delay 2 120 70 80 ns t phqv rp# to output delay 1.5 0.4 5 0.4 5 m s t glqv oe# to output delay 2 65 30 35 ns t elqx ce# to output in low z 3 0 0 0 ns t ehqz ce# to output in high z 3 55 20 25 ns t glqx oe# to output in low z 3 0 0 0 ns t ghqz oe# to output in high z 3 45 20 25 ns t oh output hold from address, ce#, or oe# change, whichever occurs first 3 0 0 0 ns t elfl t elfh ce# low to byte# high or low 3 5 5 5 ns t avfl address to byte# high or low 3 5 5 5 ns t flqv t fhqv byte# to output delay 3,4 120 70 80 ns t flqz byte# low to output in high z 3 45 20 25 ns
e 8-mbit smartvoltage boot block flash memory family 45 product preview table 13. ac characteristics: read only operations (commercial) (continued) prod bv-120 sym parameter v cc 3.30.3v (5) 5v10% (7) units load 50 pf 100 pf notes min max min max t avav read cycle time 150 120 ns t avqv address to output delay 150 120 ns t elqv ce# to output delay 2 150 120 ns t phqv rp# to output delay 1.5 0.45 s t glqv oe# to output delay 2 90 40 ns t elqx ce# to output in low z 3 0 0 ns t ehqz ce# to output in high z 3 80 30 ns t glqx oe# to output in low z 3 0 0 ns t ghqz oe# to output in high z 3 60 30 ns t oh output hold from address, ce#, or oe# change, whichever occurs first 3 0 0 ns t elfl t elfh ce# low to byte# high or low 3 5 5 ns t avfl address to byte# high or low 3 5 5 ns t flqv t fhqv byte# to output delay 3,4 150 120 ns t flqz byte# low to output in high z 3 60 30 ns notes: 1. see ac input/output reference waveform for timing measurements. 2. oe# may be delayed up to t ce ?t oe after the falling edge of ce# without impact on t ce . 3. sampled, but not 100% tested. 4. t flqv , byte# switching low to valid output delay will be equal to t avqv , measured from the time dq 15 /a ?1 becomes valid. 5. see test configurations (figure 11), 3.3v standard test component values. 6. see test c onfigurations (figure 11), 5v high-speed test component values. 7. see test configurations (figure 11), 5v standard test component values.
8-mbit smartvoltage boot block flash memory family e 46 product preview address stable device and address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) data (d/q) ih v il v rp#(p) ol v oh v phqv t high z valid output data valid standby avav t ehqz t ghqz t oh t glqv t glqx t elqv t elqx t avqv t high z 0539_14 figure 12 . ac waveforms for read operations a d d r e s s s t a b l e d e v i c e a d d r e s s s e l e c t i o n i h v i l v a d d r e s s e s ( a ) i h v i l v i h v i l v i h v i l v c e # ( e ) o e # ( g ) b y t e # ( f ) d a t a ( d / q ) ( d q 0 - d q 7 ) o l v o h v h i g h z d a t a o u t p u t o n d q 0 - d q 7 d a t a v a l i d s t a n d b y a v a v t e h q z t g h q z t a v q v t h i g h z g l q v t e l q v t a v q v t o h t d a t a o u t p u t o n d q 0 - d q 7 d a t a ( d / q ) ( d q 8 - d q 1 4 ) o l v o h v h i g h z d a t a o u t p u t o n d q 8 - d q 1 4 h i g h z ( d q 1 5 / a - 1 ) o l v o h v h i g h z h i g h z d a t a o u t p u t o n d q 1 5 a d d r e s s i n p u t f l q z t e l q x t e l f l t a v f l t g l q x t 0539_15 figure 13 . byte# timing diagram for read operations
e 8-mbit smartvoltage boot block flash memory family 47 product preview table 14. ac characteristics: we#?controlled write operations (1) (commercial) prod bv-70
8-mbit smartvoltage boot block flash memory family e 48 product preview table 14. ac characteristics: we#?controlled write operations (1) (commercial) symbo l parameter v cc 3.30.3v ( 9) 5v5% (10 ) 5v10% ( 11) unit loa d 50 pf 30 pf 100 pf note s mi n ma x mi n ma x mi n ma x t avav write cycle time 120 70 80 ns t phwl rp# setup to we# going low 1.5 0.4 5 0.4 5 m s t elwl ce# setup to we# going low 0 0 0 ns t phhwh boot block lock setup to we# going high 6,8 200 100 100 ns t vpwh v pp setup to we# going high 5,8 200 100 100 ns t avwh address setup to we# going high 3 90 50 50 ns t dvwh data setup to we# going high 4 90 50 50 ns t wlwh we# pulse width 90 50 50 ns t whdx data hold time from we# high 4 0 0 0 ns t whax address hold time from we# high 3 0 0 0 ns t wheh ce# hold time from we# high 0 0 0 ns t whwl we# pulse width high 20 10 20 ns t whqv1 duration of word/byte programming operation 2,5 6 6 6 s t whqv2 duration of erase operation (boot) 2,5,6 0.3 0.3 0.3 s t whqv3 duration of erase operation (parameter) 2,5 0.3 0.3 0.3 s
e 8-mbit smartvoltage boot block flash memory family 49 product preview table 14. ac characteristics: we#?controlled write operations (1) (commercial) t whqv4 duration of erase operation (main) 2,5 0.6 0.6 0.6 s t qwl v pp hold from valid srd 5,8 0 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 0 ns t phbr boot-block lock delay 7,8 200 100 100 ns
8-mbit smartvoltage boot block flash memory family e 50 product preview table 14. ac characteristics: we#?controlled write operations (1) (commercial) (continued) prod bv-120 sym parameter v cc 3.30.3v (9) 5v10% (11) unit load 50 pf 100 pf note min max min max t avav write cycle time 180 120 ns t phwl rp# setup to we# going low 1.5 0.45 s t elwl ce# setup to we# going low 0 0 ns t phhwh boot block lock setup to we# going high 6,8 200 100 ns t vpwh v pp setup to we# going high 5,8 200 100 ns t avwh address setup to we# going high 3 150 50 ns t dvwh data setup to we# going high 4 150 50 ns t wlwh we# pulse width 150 50 ns t whdx data hold time from we# high 4 0 0 ns t whax address hold time from we# high 3 0 0 ns t wheh ce# hold time from we# high 0 0 ns t whwl we# pulse width high 30 30 ns t whqv1 duration of word/byte programming operation 2,5 6 6 s t whqv2 duration of erase operation (boot) 2,5,6 0.3 0.3 s t whqv3 duration of erase operation (parameter) 2,5 0.3 0.3 s t whqv4 duration of erase operation (main) 2,5 0.6 0.6 s t qwl v pp hold from valid srd 5,8 0 0 ns
e 8-mbit smartvoltage boot block flash memory family 51 product preview t qvph rp# v hh hold from valid srd 6,8 0 0 ns t phbr boot-block lock delay 7,8 200 100 ns notes: 1. read timing characteristics during write and erase operations are the same as during read-only operations. refer to ac characteristics during read mode. 2. the on-chip wsm completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. refer to command definition table for valid a in . (table 7 ) 4. refer to command definition table for valid d in . (table 7 ) 5. program/erase durations are measured to valid srd data (successful operation, sr.7=1). 6. for boot block program/erase, rp# should be held at v hh or wp# should be held at v ih until operation completes successfully. 7. time t phbr is required for successful locking of the boot block. 8. sampled, but not 100% tested. 9. see test configurations (figure 11), 3.3v standard test component values.) 10. see test configurations (figure 11), 5v high-speed test component values. 11. see test configurations (figure 11), 5v standard test component values. a d d r e s s e s ( a ) c e # ( e ) o e # ( g ) w e # ( w ) d a t a ( d / q ) r p # ( p ) i h v i l v i h v i l v i h v i l v i h v i l v h h v 6 . 5 v i l v i l v i n d i n a i n a w h e h t w h w l t v a l i d s r d i n d w h q v 1 , 2 , 3 , 4 t p h h w h t i h v p h w l t h i g h z w h d x t i h v i l v v ( v ) p p 1 2 3 4 6 5 p p h v p p l k v p p h v 1 2 w p # i l v i h v a v a v t a v w h t w h a x t d v w h t w l w h t q v p h t q v v l t v p w h t i n d e l w l t 0539_16 figure 14 . ac waveforms for write and erase operations (we#?controlled writes)
8-mbit smartvoltage boot block flash memory family e 52 product preview table 15. ac characteristics: ce#?controlled write operations (1,12) (commercial) prod bv-70 v cc 3.30.3v ( 9) 5v5% (10 ) 5v10% ( 11) symbo l parameter loa d 50 pf 30 pf 100 pf unit note min max min max min max t avav write cycle time 120 70 80 ns t phel rp# high recovery to ce# going low 1.5 0.4 5 0.4 5 s t wlel we# setup to ce# going low 0 0 0 ns t phheh boot block lock setup to ce# going high 6,8 200 100 100 ns t vpeh v pp setup to ce# going high 5,8 200 100 100 ns t aveh address setup to ce# going high 3 90 50 50 ns t dveh data setup to ce# going high 4 90 50 50 ns t eleh ce# pulse width 90 50 50 ns t ehdx data hold time from ce# high 4 0 0 0 ns t ehax address hold time from ce# high 3 0 0 0 ns t ehwh we # hold time from ce# high 0 0 0 ns t ehel ce# pulse width high 20 10 20 ns t ehqv1 duration of word/byte programming operation 2,5 6 6 6 s t ehqv2 duration of erase operation (boot) 2,5,6 0.3 0.3 0.3 s
e 8-mbit smartvoltage boot block flash memory family 53 product preview table 15. ac characteristics: ce#?controlled write operations (1,12) (commercial) t ehqv3 duration of erase operation (parameter) 2,5 0.3 0.3 0.3 s t ehqv4 duration of erase operation (main) 2,5 0.6 0.6 0.6 s t qwl v pp hold from valid srd 5,8 0 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 0 ns t phbr boot-block lock delay 7,8 200 100 100 ns table 15. ac characteristics: ce#?controlled write operations (1,12) (commercial) (continued) prod bv-120 sym parameter v cc 3.30.3v (9) 5v10% (11) unit load 50 pf 100 pf note min max min max t avav write cycle time 180 120 ns t phel rp# high recovery to ce# going low 1.5 0.45 m s t wlel we# setup to ce# going low 0 0 ns t phheh boot block lock setup to ce# going high 6,8 200 100 ns t vpeh v pp setup to ce# going high 5,8 200 100 ns t aveh address setup to ce# going high 3 150 50 ns t dveh data setup to ce# going high 4 150 50 ns t eleh ce# pulse width 150 50 ns t ehdx data hold time from ce# high 4 0 0 ns t ehax address hold time from ce# high 3 0 0 ns t ehwh we # hold time from ce# high 0 0 ns t ehel ce# pulse width high 30 30 ns
8-mbit smartvoltage boot block flash memory family e 54 product preview t ehqv1 duration of word/byte programming operation 2,5 6 6 s t ehqv2 duration of erase operation (boot) 2,5,6 0.3 0.3 s t ehqv3 duration of erase operation (parameter) 2,5 0.3 0.3 s t ehqv4 duration of erase operation (main) 2,5 0.6 0.6 s t qwl v pp hold from valid srd 5,8 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 ns t phbr boot-block lock delay 7,8 200 100 ms notes: see we# controlled write operations for notes 1 through 11. 12. chip-enable controlled writes: write operations are driven by the valid combination of ce# and we# in systems where ce# defines the write pulse-width (within a longer we# timing waveform), all set-up, hold and inactive we# times should be measured relative to the ce# waveform.
e 8-mbit smartvoltage boot block flash memory family 55 product preview a d d r e s s e s ( a ) w e # ( w ) o e # ( g ) c e # ( e ) d a t a ( d / q ) r p # ( p ) i h v i l v i h v i l v i h v i l v i h v i l v h h v 6 . 5 v i l v i n d i n a i n a a v a v t v a l i d s r d i n d q v p h t p h h e h t h i g h z e h d x t i h v i l v v ( v ) p p 1 2 3 4 6 5 e h a x t e h q v 1 , 2 , 3 , 4 t e h e l t e h w h t e l e h t d v e h t v p e h t q v v l t p h e l t w l e l t a v e h t p p l k v p p h v 1 2 p p h v i l v i h v i l v i h v w p # i n d 0539_17 notes: 1. v cc power-up and standby. 2. write program or erase setup command. 3. write valid address and data (program) or erase confirm command. 4. automated program or erase delay. 5. read status register data. 6. write read array command. figure 15 . alternate ac waveforms for write and erase operations (ce#?controlled writes)
8-mbit smartvoltage boot block flash memory family e 56 product preview table 16. erase and program timings (commercial t a = 0c to +70c) v pp 5v 10% 12v 5% parameter v cc 3.3 0.3v 5v 10% 3.3 0.3v 5v 10% un it typ max typ max typ max typ max boot/parameter block erase time 0.84 7 0.8 7 0.44 7 0.34 7 s main block erase time 2.4 14 1.9 14 1.3 14 1.1 14 s main block write time (byte mode) 1.7 1.8 1.6 1.2 s main block write time (word mode) 1.1 0.9 0.8 0.6 s byte write time 10 10 8 8 s word write time 13 13 8 8 s notes: 1. all numbers are sampled, not 100% tested. 2. max erase times are specifi ed under worst case conditions. the max erase times are tested at the same value independent of v cc and v pp . see note 3 for typical conditions. 3. typical conditions are 25c with v cc and v pp at the center of the specifed voltage range. production programming using v cc = 5.0v, v pp = 12.0v typically results in a 60% reduction in programming time. 4. contact your intel representative for information regarding maximum byte/word write specifications.
e 8-mbit smartvoltage boot block flash memory family 57 product preview 6. 0 extended operating conditions table 17. extended temperature and v cc operating conditions symbol parameter notes min max units t a operating temperature ?40 +85 c v cc 2.7v?3.6v v cc supply voltage 1 2.7 3.6 volts 3.3v v cc supply voltage ( 0.3v) 1 3.0 3.6 volts 5v v cc supply voltage (10%) 2 4.50 5.50 volts notes: 1. ac specifications are valid at both voltage ranges. see dc characteristics tables for voltage range-specific specifications. 2. 10% v cc specifications apply to 100 ns versions in their standard test configuration. 6.1 applying v cc voltages when applying v cc voltage to the device, a delay may be required before initiating device operation, depending on the v cc ramp rate. if v cc ramps slower than 1v/100 s (0.01 v/s) then no delay is required. if v cc ramps faster than 1v/100 s (0.01 v/s), then a delay of 2 s is required before initiating device opeation. rp# = gnd is recommended during power- up to protect against spurious write signals when v cc is between v lko and v ccmin . v cc ramp rate required timing 1v/100 m s no delay required. > 1v/100 m s a delay time of 2 m s is required before any device operation is initiated, including read operations, command writes, program operations, and erase operations. this delay is measured beginning from the time v cc reaches v ccmin (2.7v for 2.7v?3.6v operation, 3.0v for 3.3 0.3v operation; and 4.5v for 5v operation). notes: 1. these requirements must be strictly followed to guarantee all other read and write specifications. 2. to switch between 3.3v and 5v operation, the system should first transition v cc from the existing voltage range to gnd, and then to the new voltage. any time the v cc supply drops below v ccmin , the chip may be reset, aborting any operations pending or in progress. 3. these guidelines must be followed for any v cc transition from gnd.
8-mbit smartvoltage boot block flash memory family e 58 product preview 6.2 dc characteristics table 18. dc characteristics: extended temperature operation prod tbe-120 tbv-90 tbv-90 tbe-120 sym paramet er v cc 2.7v?3.6v 3.3v 0.3v 5v 10% unit test conditions note s typ ma x typ ma x typ ma x i il input load current 1 1.0 1.0 1.0 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 10 10 a v cc = v cc max v in = v cc or gnd i ccs v cc standby current 1,3 50 110 60 110 70 150 a cmos levels v cc = v cc max ce# = rp# = wp# = v cc 0.2v 0.4 1.5 0.4 1.5 0.8 2.5 ma ttl levels v cc = v cc max ce# = rp# = byte# = v ih i ccd v cc deep power- down current 1 0.2 8 0.2 8 0.2 8 a v cc = v cc max v in = v cc or gnd rp# = gnd 0.2v
e 8-mbit smartvoltage boot block flash memory family 59 product preview table 18. dc characteristics: extended temperature operation i ccr v cc read current for word or byte 1,5,6 14 30 15 30 50 65 ma cmos inputs v cc = v cc max ce = v il f = 10 mhz (5v) 5 mhz (3.3v) i out = 0 ma inputs = gnd 0.2v or v cc 0.2v 14 30 15 30 55 70 ma ttl inputs v cc = v cc max ce# = v il f = 10 mhz (5v), 5 mhz (3.3v) i out = 0 ma inputs = v il or v ih
8-mbit smartvoltage boot block flash memory family e 60 product preview table 18. dc characteristics: extended temperature operation (continued) prod tbe-120 tbv-90 tbv-90 tbe-120 sym paramet er v cc 2.7v?3.6v 3.3v 0.3v 5v 10% unit test conditions note s typ ma x typ ma x typ ma x i ccw v cc write current for word or byte 1,4 8 30 13 30 30 50 ma v pp = v pph 1 (at 5v) word/byte program in progress 9 25 10 25 30 45 ma v pp = v pph 2 (at 12v) word/byte program in progress i cce v cc erase current 1,4 12 30 13 30 22 45 ma v pp = v pph 1 (at 5v) block erase in progress 9 25 10 25 18 40 ma v pp = v pph 2 (at 12v) block erase in progress i cces v cc erase suspend current 1,2 2.5 8.0 3 8.0 5 12.0 ma v pp = v pph 1 (at 5v) ce# = v ih block erase suspend i pps v pp standby current 1 5 15 5 15 5 15 a v pp < v pph 2 i ppd v pp deep power- down current 1 0.2 10 0.2 10 0.2 10 a rp# = gnd 0.2v
e 8-mbit smartvoltage boot block flash memory family 61 product preview table 18. dc characteristics: extended temperature operation (continued) i ppr v pp read current 1 50 200 50 200 50 200 a v pp 3 v pph 2 i ppw v pp write current for word/byt e 1,4 13 30 13 30 13 30 ma v pp = v pph word write in progress v pp = v pph 1 (at 5v) 8 25 8 25 8 25 ma v pp = v pph word write in progress v pp = v pph 2 (at 12v)
8-mbit smartvoltage boot block flash memory family e 62 product preview table 18. dc characteristics: extended temperature operation (continued) prod tbe-120 tbv-90 tbv-90 tbe-120 sym paramet er v cc 2.7v?3.6v 3.3v 0.3v 5v 10% unit test conditions note s typ ma x typ ma x typ ma x i ppe v pp erase current 1,4 13 30 13 30 15 25 ma v pp = v pph block erase in progress v pp = v pph 1 (at 5v) 8 25 8 25 10 20 ma v pp = v pph block erase in progress v pp = v pph 2 (at 12v) i ppes v pp erase suspend current 1 50 200 50 200 50 200 a v pp = v pph block erase suspend in progress i rp# rp# boot block unlock current 1,4 500 500 500 a rp# = v hh v pp = 12v i id a 9 intelligen t identifier current 1,4 500 500 500 a a 9 = v id
e 8-mbit smartvoltage boot block flash memory family 63 product preview table 18. dc characteristics: extended temperature operation (continued) prod tbe-120 tbv-90 tbv-90 tbe-120 sym paramet er v cc 2.7v? 3.6v 3.3v 0.3v 5v 10% unit test conditions note s min ma x min ma x mi n ma x v id a 9 intelligen t identifier voltage 11.4 12. 6 11.4 12.6 11. 4 12.6 v v il input low voltage ?0.5 0.8 ?0.5 0.8 ? 0.5 0.8 v v ih input high voltage 2.0 v cc 0.5 v 2.0 v cc 0.5 v 2.0 v cc 0.5 v v v ol output low voltage 0.4 5 0.45 0.45 v v cc = v cc min v pp = 12v i ol = 5.8 ma (5v) 2 ma (3.3v) v oh 1 output high voltage (ttl) 2.4 2.4 2.4 v v cc = v cc min i oh = ?2.5 ma v oh 2 output high voltage 0.85 5 v cc 0.85 5 v cc 0.8 5 5 v cc v v cc = v cc min i oh = ?2.5 ma (cmos) v cc ? 0.4 v v cc ? 0.4v v cc ? 0.4 v v cc = v cc min i oh = ?100 a
8-mbit smartvoltage boot block flash memory family e 64 product preview table 18. dc characteristics: extended temperature operation (continued) v ppl k v pp lock-out voltage 3 0.0 1.5 0.0 1.5 0.0 1.5 v complete write protection v pph 1 v pp during prog/eras e operation s 4.5 5.5 4.5 5.5 4.5 5.5 v v pp at 5v v pph 2 11.4 12. 6 11.4 12.6 11. 4 12.6 v v pp at 12v v lko v cc erase/wri te lock voltage 8 2.0 2.0 2.0 v v hh rp# unlock voltage 11.4 12. 6 11.4 12.6 11. 4 12.6 v boot block write/ erase v pp = 12v table 19. capacitance (t a = 25 c, f = 1 mhz) symbol parameter notes typ max units conditions c in input capacitance 4 6 8 pf v in = 0v c out output capacitance 4 10 12 pf v out = 0v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0v, t = +25c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with device de-selected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . 3. block erases and word/byte writes inhibited when v pp = v pplk , and not guaranteed in the range between v pph 1 and v pplk . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to less than 1 ma typical, in static operation. 6. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 7. for the 28f008b a ddress pin a 10 follows the c out capacitance numbers. 8. for all bv/cv/be/ce parts, v lko = 2.0v for 2.7v, 3.3v and 5.0v operations.
e 8-mbit smartvoltage boot block flash memory family 65 product preview test points input output 1 . 3 5 2 . 7 0 . 0 1 . 3 5 0539_18 note: ac test inputs are driven at 2.7 for a logic ?1? and 0.0v for a logic ?0.? input timing begins, and output timing ends, at 1.35v. input rise and fall times (10%?90%) <10 ns. figure 16 . 2.7?3.6v input range and measurement points test points input output 1 . 5 3 . 0 0 . 0 1 . 5 0539_09 note: ac test inputs are driven at 3.0v for a logic ?1? and 0.0v for a logic ?0.? input timing begins, and output timing ends, at 1.5v. input rise and fall times (10%?90%) <10 ns. figure 17 . 3.3v input range and measurement points test points input output 2.0 0.8 0.8 2.0 2.4 0.45 0539_10 note: ac test inputs are driven at v oh (2.4 v ttl ) for a logic ?1? and v ol (0.45 v ttl ) for a logic ?0.? input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ) . output timing ends at v ih and v il . input rise and fall times (10%?90%) < 10 ns. figure 18 . 5v input range and measurement points
8-mbit smartvoltage boot block flash memory family e 66 product preview c l o u t v c c d e v i c e u n d e r t e s t r 1 r 2 0539_11 note: see table for component values. figure 19 . test configuration test configuration component values test configuration c l (pf) r 1 ( w w ) r 2 ( w w ) 2.7v and 3.3v standard test 50 990 770 5v standard test 100 580 390 note: c l includes jig capacitance.
e 8-mbit smartvoltage boot block flash memory family 67 product preview 6.3 ac characteristics table 20. ac characteristics: read only operations (1) (extended temperature) prod tbe-120 tbv-90 tbv-90 tbe-120 sym parameter v cc 2.7? 3.6v (5) 3.30.3v ( 5) 5v10% ( 6) unit s loa d 50 pf 50 pf 100 pf note s mi n ma x mi n ma x mi n ma x t avav read cycle time 120 120 90 ns t avqv address to output delay 120 120 90 ns t elqv ce# to output delay 2 120 120 90 ns t phqv rp# to output delay 1.5 1.5 0.4 5 m s t glqv oe# to output delay 2 65 65 40 ns t elqx ce# to output in low z 3 0 0 0 ns t ehqz ce# to output in high z 3 55 55 30 ns t glqx oe# to output in low z 3 0 0 0 ns t ghqz oe# to output in high z 3 45 45 30 ns t oh output hold from address, ce#, or oe# change, whichever occurs first 3 0 0 0 ns t elfl t elfh ce# low to byte# high or low 3 5 5 5 ns t avfl address to byte# high or low 3 5 5 5 ns t flqv t fhqv byte# to output delay 3,4 120 120 90 ns t flqz byte# low to output in high z 3 45 45 30 ns notes:
8-mbit smartvoltage boot block flash memory family e 68 product preview 1. see ac input/output reference waveform for timing measurements. 2. oe# may be delayed up to t ce ?t oe after the falling edge of ce# without impact on t ce . 3. sampled, but not 100% tested. 4. t flqv , byte# switching low to valid output delay will be equal to t avqv , measured from the time dq 15 /a ? 1 becomes valid. 5. see test configurations (figure 19), 2.7?3.6v and 3.3 0.3v standard test component values. 6. see test configurations (figure 19), 5v standard test component values.
e 8-mbit smartvoltage boot block flash memory family 69 product preview table 21. ac characteristics: we#-controlled write operations (1) (extended temperature) prod tbe-120 tbv-90 tbv-90 tbe-120 sym parameter v cc 2.7? 3.6v (9) 3.30.3v ( 9) 5v10% ( 10) units loa d 50 pf 50 pf 100 pf note s mi n ma x mi n ma x mi n ma x t avav write cycle time 120 120 90 ns t phwl rp# high recovery to we# going low 1.5 1.5 0.4 5 m s t elwl ce# setup to we# going low 0 0 0 ns t phhwh boot block lock setup to we# going high 6,8 200 200 100 ns t vpwh v pp setup to we# going high 5,8 200 200 100 ns t avwh address setup to we# going high 3 90 90 60 ns t dvwh data setup to we# going high 4 70 70 60 ns t wlwh we# pulse width 90 90 60 ns t whdx data hold time from we# high 4 0 0 0 ns t whax address hold time from we# high 3 0 0 0 ns t wheh ce# hold time from we# high 0 0 0 ns t whwl we# pulse width high 30 20 20 ns
8-mbit smartvoltage boot block flash memory family e 70 product preview table 21. ac characteristics: we#-controlled write operations (1) (extended temperature) t whqv1 duration of word/byte write operation 2,5,8 6 6 6 s t whqv2 duration of erase operation (boot) 2,5,6 , 8 0.3 0.3 0.3 s t whqv3 duration of erase operation (parameter) 2,5,8 0.3 0.3 0.3 s t whqv4 duration of erase operation (main) 2,5,8 0.6 0.6 0.6 s
e 8-mbit smartvoltage boot block flash memory family 71 product preview table 21. ac characteristics: we#-controlled write operations (1) (extended temperature) (continued) prod tbe-120 tbv-90 tbv-90 tbe-120 sym parameter v cc 2.7? 3.6v (9) 3.30.3v ( 9) 5v10% ( 10) unit loa d 50 pf 50 pf 100 pf note s mi n ma x mi n ma x mi n ma x t qwl v pp hold from valid srd 5,8 0 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 0 ns t phbr boot-block lock delay 7,8 200 200 100 ns notes: 1. read timing characteristics during write and erase operations are the same as during read-only operations. refer to ac characteristics during read mode. 2. the on-chip wsm completely automates program/erase operations; program/erase algori thms are now controlled internally which includes verify and margining operations. 3. refer to command definition table for valid a in . (table 7 ) 4. refer to command definition table for valid d in . (table 7 ) 5. program/erase durations are measured to valid srd data (successful operation, sr.7 = 1) 6. for boot block program/erase, rp# should be held at v hh or wp# should be held at v ih until operation completes successfully. 7. time t phbr is required for successful locking of the boot block. 8. sampled, but not 100% tested. 9. see test configurations (figure 19), 2.7?3.6v and 3.3 0.3v standard test component values. 10. see test configurations (figure 19), 5v standard test component values.
8-mbit smartvoltage boot block flash memory family e 72 product preview table 22. ac characteristics: ce#?controlled write operations (1,11) (extended temperature) prod tbe-120 tbv-90 tbv-90 tbe-120 sym parameter v cc 2.7? 3.6v (9) 3.30.3v ( 9) 5v10% ( 10) unit loa d 50 pf 50 pf 100 pf note s mi n ma x mi n ma x mi n ma x t avav write cycle time 120 120 90 ns t phel rp# high recovery to ce# going low 1.5 1.5 0.4 5 m s t wlel we# setup to ce# going low 0 0 0 ns t phheh boot block lock setup to ce# going high 6,8 200 200 100 ns t vpeh v pp setup to ce# going high 5,8 200 200 100 ns t aveh address setup to ce# going high 90 90 60 ns t dveh data setup to ce# going high 3 70 70 60 ns t eleh ce# pulse width 4 90 90 60 ns t ehdx data hold time from ce# high 0 0 0 ns t ehax address hold time from ce# high 4 0 0 0 ns t ehwh we# hold time from ce# high 3 0 0 0 ns t ehel ce# pulse width high 20 20 20 ns t ehqv1 duration of word/byte write operation 2,5 6 6 6 s
e 8-mbit smartvoltage boot block flash memory family 73 product preview table 22. ac characteristics: ce#?controlled write operations (1,11) (extended temperature) t ehqv2 duration of erase operation (boot) 2,5,6 0.3 0.3 0.3 s t ehqv3 duration of erase operation (parameter) 2,5 0.3 0.3 0.3 s t ehqv4 duration of erase operation (main) 2,5 0.6 0.6 0.6 s t qwl v pp hold from valid srd 5,8 0 0 0 ns t qvph rp# v hh hold from valid srd 6,8 0 0 0 ns t phbr boot-block lock delay 7,8 200 200 100 ns notes: see we# controlled write operations for notes 1 through 10. 11. chip-enable controlled writes: write operations are driven by the valid combination of ce# and we# in systems where ce# defines the write pulse-width (within a longer we# timing waveform), all set-up, hold and inactive we# times should be measured relative to the ce# waveform.
8-mbit smartvoltage boot block flash memory family e 74 product preview table 23. extended temperature operations - erase and program timings v pp 5v 10% 12v 5% v cc 2.7?3.6v 3.3 0.3v 5v 10% 2.7?3.6v 3.3 0.3v 5v 10% parameter typ ma x typ ma x typ ma x typ ma x typ ma x typ ma x un it boot/parameter block erase time 0.88 tb d 0.84 7 0.8 7 0.46 tb d 0.44 7 0.34 7 s main block erase time 2.5 tb d 2.4 14 1.9 14 1.36 tb d 1.3 14 1.1 14 s main block write time (byte mode) 1.87 1.7 1.4 1.76 1.6 1.2 s main block write time (word mode) 1.21 1.1 0.9 0.88 0.8 0.6 s byte write time 11 10 10 8.8 8 8 s word write time 14.3 13 13 8.8 8 8 s notes: 1. all numbers are sampled, not 100% tes ted. 2. max erase times are specified under worst case conditions. the max erase times are tested at the same value independent of v cc and v pp . see note 3 for typical conditions. 3. typical conditions are 25c with v cc and v pp at the center of the specifed voltage range. production programming using v cc = 5.0v, v pp = 12.0v typically results in a 60% reduction in programming time. 4. contact your intel representative for information regarding maximum byte/word write specifications.
e 8-mbit smartvoltage boot block flash memory family 75 product preview 7. 0 additi onal information 7.1 ordering information
8-mbit smartvoltage boot block flash memory family e 76 product preview p r o d u c t l i n e d e s i g n a t o r f o r a l l i n t e l f l a s h p r o d u c t s d e n s i t y / o r g a n i z a t i o n 0 0 x = x 8 - o n l y ( x = 1 , 2 , 4 , 8 ) x 0 0 = x 8 / x 1 6 s e l e c t a b l e ( x = 2 , 4 , 8 ) a c c e s s s p e e d n s , b e : v = 2 . 7 v b v : v = 5 v a r c h i t e c t u r e b = b o o t b l o c k c = c o m p a c t 4 8 - l e a d t s o p b o o t b l o c k o p e r a t i n g t e m p e r a t u r e t = e x t e n d e d t e m p b l a n k = c o m m e r c i a l t e m p p a c k a g e e = t s o p p a = 4 4 - l e a d p s o p t b = e x t . t e m p 4 4 - l e a d p s o p e 2 8 f 8 0 0 c v - t 0 7 t = t o p b o o t b = b o t t o m b o o t c c c c v o l t a g e o p t i o n s ( v / v ) v = ( 5 o r 1 2 / 3 . 3 o r 5 ) e = ( 5 o r 1 2 / 2 . 7 o r 5 ) p p c c 0530-23 valid combinations: 40-lead tsop 44-lead psop 48-lead tsop commercial e28f008bvt70 pa28f800bvt70 e28f800cvt70 e28f008bvb70 pa28f800bvb70 e28f800cvb70 e28f008bvt120 pa28f800bvt120 e28f008bvb120 pa28f800bvb120 extended te28f008bvt90 tb28f800bvt90 te28f800cvt90 te28f008bvb90 tb28f800bvb90 te28f800cvb90 te28f008bet120 te28f800cet120 te28f008beb120 te28f800ceb120 table 24. summary of line items name v cc v pp package temperature 2.7?3.6 3.30.3 5 10% 5 10% 12 5% 40-ld tsop 44-ld psop 48-ld tsop comm ext 28f008 bv ? ? ? ? ? ? ? 28f800 bv ? ? ? ? ? ? ? ? 28f800 cv ? ? ? ? ? ? ? 28f008 be ? ? ? ? ? ? ? 28f800 ce ? ? ? ? ? ? ?
e 8-mbit smartvoltage boot block flash memory family 77 product preview 7.2 references order number document 290531 2-mbit smartvoltage boot block flash memory family datasheet 290530 4-mbit smartvoltage boot block flash memory family datasheet 290448 28f002/200bx-t/b 2-mbit boot block flash memory datasheet 290449 28f002/200bl-t/b 2-mbit low power boot block flash memory datasheet 290450 28f004/400bl-t/b 4-mbit low power boot block flash memory datasheet 290451 28f004/400bx-t/b 4-mbit boot block flash memory datasheet 292148 ap-604 ?using intel?s boot block flash memory parameter blocks to replace eeprom? 292172 ap-617 ?additional flash data protection using v pp , rp#, and wp#? 292130 ab-57 ?boot block architecture for safe firmware updates? 292154 ab-60 ?2/4/8 -mbit smartvoltage boot block flash memory family? 7.3 revision history -001 initial release of datasheet, no specifications included -002 explanation of wp# on 44-lead psop added; ac/dc specifications added, including be product text and 2.7v specifications. -003 28f800be row removed from table 1 applying v cc voltages (sections 5.1 and 6.1) rewritten for clarity. minor cosmetic changes/edits.

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